In an effort to deal with and simplify otherwise extremely complex design rules at advanced process rules, foundries are now turning to a different approach in which routing regions of a design on any particular metal layer are performed only on a set of specific metal tracks, each of which may only take on width values from a discrete set of legal widths that may be made available in the process Design Rule Manual (DRM). Furthermore, in order to facilitate self-aligned double patterning (SADP) processes and deal with mask designation issues, additional constraints may be created by which track widths may be selected. For example, after a first track is chosen and assigned a photomask color or photomask designation (e.g. B for Blue), the next track may need to be assigned a different photomask color or photomask designation (e.g., C for Cyan), and may only take one of a discrete set of legal width values, where that set in turn is a function of the preceding B track width.
An electronic design may correspond to and thus include more than ten different size wires, and the tracks for the electronic design may thus be associated with as many legal widths. Any attempt to manually figure out which track associated with a given width may be immediately neighboring another track associated with a given width is nearly impossible due to the sheer number of different possible legal combinations of tracks, especially in light of the extremely complex design rules that govern what track patterns are legal. Therefore, generating a legal track pattern including a plurality of tracks associated with some legal widths is nearly impossible to be performed manually, especially when an electronic design includes more than a few legal or permissible widths.
Therefore, there exists a need for effective and efficient techniques to implement track pattern for electronic circuit designs.